Pwm control system

ABSTRACT

A PWM control system, comprising PWM fundamental wave generation means for forming a PWM fundamental wave by dividing a fundamental frequency signal; PWM cycle setting means for setting a PWM cycle on the basis of the PWM fundamental wave; duty ratio formation means for forming a duty ratio (N/M:N≦M, where M is the maximum number of clocks) in the PWM cycle; and PWM control signal output means for outputting a PWM control signal with the duty ratio to a load drive circuit.

CROSS-REFERENCES

The present invention relates to a PWM control system. The PWM controlsystem of the present invention can be used for drive-controlling avariety of loads such as AC motors and DC motors including pulse motors.The PWM drive control system of the present invention can be widelyapplied as long as the drive circuit of the load can be drive-controlledusing a duty ratio in accordance with the operating state of the loadthat is the target of control such as motor control, display devicecontrol, speech output control, oscillation control, touch sensitivitycontrol, atomization control, and mixing control.

BACKGROUND

Conventionally, a PWM system drives a DC motor, for example, producing adrive command signal for a preset PWM cycle, setting the duty ratio ofthe drive command signal to obtain the torque required for the DC motor,and causing a switching element to perform switching.

In a system block of a DC motor drive apparatus, a CPU for controllingthe whole of the DC motor and a PWM control section that receivescommands from the CPU via a system bus and produces a drive commandsignal are provided. The duty ratio of the drive command signal is setto be proportional to the torque required for the DC motor.

Further, Japanese Patent Application Laid Open No. H7-163189, forexample, mentions a PWM motor control system using a switching signalthat compares a reference signal with a predetermined waveform that istriangular or the like and a command signal for the motor andPWM-modulates the reference signal by means of the command signal.

In addition, Japanese Patent Application Laid Open No. 2000-37079discloses a PWM circuit comprising a CPU that sets control informationand the output of a signal wave constituting a command value based on asignal wave reference signal that is inputted from outside, a PLLcircuit to which the signal wave reference signal is inputted thatoutputs a phase reference signal indicating that a pulse the frequencyof which is a fixed multiple of the frequency of the signal wavereference signal and a signal wave reference signal have reached aspecified phase, a divider that divides the pulse outputted by the PLLcircuit at a division ratio that is preset by the CPU, an up/downcounter to which the output of the divider is inputted and which sets apredetermined value that is preset at the timing of the phase referencesignal from the PLL circuit, repeats the up and down count between twopredetermined values that are set separately from the formerpredetermined value thus set, and outputs a carrier wave, a comparatorthat compares the carrier wave and signal wave and, depending on thesize of the carrier wave and signal wave, outputs a switching signalthat controls the ON/OFF of the switching element of the outputconverter, the PWM circuit comprising a first register that temporarilyholds the division ratio of the divider that is set by the CPU, and asecond register to which the temporarily held division ratio is inputtedwith the timing of the phase reference signal from the PLL circuit andwhich holds the division ratio and causes the divider to reflect thedivision ratio. In this PWM circuit, the duty ratio of the drive signalsupplied to the load is changed in accordance with the ON/OFF of theswitching signal.

SUMMARY

In order to increase the operating efficiency of a load and so forth, adrive method that allows the PWM cycle to fluctuate has becomenecessary. However, with conventional control systems, the PWM drivefrequency is used only in a fixed state. Further, an analog circuit forproducing a sawtooth wave is required by a conventional PWM controlsystem.

Therefore, in order to solve this problem, an object of the presentinvention is to provide a PWM control system that that allows the PWMcycle to be changed, the duty ratio to be set in accordance with theoperating state of the load, and which permits formation using fulllogic.

In order to achieve this object, the present invention is a PWM controlsystem, comprising PWM fundamental wave generation means for forming aPWM fundamental wave by dividing a fundamental frequency signal; PWMcycle setting means for setting a PWM cycle on the basis of the PWMfundamental wave; duty ratio setting means for setting a duty ratio(N/M:N≦M, where M is the maximum number of clocks) for each single cycleof the PWM; and PWM control signal output means for outputting a PWMcontrol signal with the duty ratio to a load drive circuit.

In an embodiment of the present invention, the PWM cycle setting meanssets a number of clocks corresponding with the M value of the PWMfundamental wave as the PWM cycle. The PWM control system furthercomprises control characteristic setting means for determining thedivision value (M) and duty ratio set value (N) in accordance with theoperating state of the load. The PWM fundamental wave generation meansforms a PWM fundamental frequency signal by M-dividing the fundamentalfrequency signal by means of a PLL circuit. The PWM control signaloutput means outputs the AC PWM control signal by switching the polarityof the outputted PWM control signal. The PWM fundamental wave generationmeans is constituted to lock the PWM cycle to the cycle of the AC drivefrequency signal.

The present invention further comprises load operating state detectionmeans; load operating state command means; a PLL circuit for dividingthe fundamental wave at a division ratio corresponding with theoperating command state; and comparing means for comparing the outputfrom the PLL circuit and the load operating state detection value,wherein the comparison result is supplied to the aforementioned PWMcontrol system, and the PWM control signal of the duty ratiocorresponding with the comparison result is outputted to the load drivecircuit.

The present invention makes it possible to perform modulation on the PWMfundamental wave to change the PWM cycle and perform modulation on thePWM fundamental wave to change the duty ratio in accordance with theoperating state of the load, and therefore changes to the PWM cycle andchanges to the duty ratio can be reliably executed without using ananalog circuit.

DESCRIPTION OF DRAWINGS

FIG. 1 is a function block diagram of a PWM control block according tothe present invention;

FIG. 2 is a waveform characteristic view of the PWM control block;

FIG. 3 is a function block diagram of a PWM control block according to asecond embodiment;

FIG. 4 is a waveform characteristic view of the PWM control blockaccording to the second embodiment;

FIG. 5 is a function block diagram of a PWM control block according to athird embodiment;

FIG. 6 is a waveform characteristic view of the PWM control blockaccording to the third embodiment;

FIG. 7 is a function block diagram showing an embodiment in which thePWM control block is used in a motor speed control system;

FIG. 8 is a waveform characteristic view of the PWM control block; and

FIG. 9 is a function block diagram in which PWM control is implementedby a personal computer.

DETAILED DESCRIPTION

FIG. 1 is a representative function block diagram of a PWM controlsystem 1 according to the present invention. This PWM control system isa drive control system of a DC motor. In FIG. 1, numeral 10 is aliquid-crystal emitter, numeral 12 is a PWM fundamental wave generationsection comprising a PLL circuit that divides the oscillation frequencyof the liquid-crystal emitter. The division efficiency is determined bya CPU 16 and set in a register 14. A clock signal (F(Hz)) of the PWMcontrol fundamental wave, the fundamental frequency clock of which isdivided by the PLL circuit, is formed.

(1) in FIG. 2 shows the clock (PWM-CLK) of the PWM control fundamentalwave. Numeral 18 in FIG. 1 is a register for control parameters forforming the PWM cycle, the parameters being established and stored asmaximum values for setting the duty ratio (described subsequently).Numeral 20 is a register for duty control parameters (N) of the PWMcontrol wave. The M and N values are established in the register by theCPU that establishes the relational characteristics of the loadoperating states and numerical values in the memory. The PWM control ofcomplex patterns can be implemented by establishing N values in anumerical value table. Further, by determining the N values from ananalog comparator, PWM control can also be implemented from an analogsignal.

(2) in FIG. 2 is an enlarged view of the clock of the PWM controlfundamental wave. When the M value for establishing a PWM cycle isdetermined by the CPU16 for controlling the whole of the system in FIG.1, as per (3), the frequency of the PWM fundamental wave is divided into(1/M) and a pulse for determining the PWM cycle is outputted for every Mpulses of the fundamental wave. As a result, the PWM cycle (T) is set asa period that is M pulses' worth of the fundamental wave (1). Further, acase where M=20 is shown in FIG. 2. The divider circuit of a PWM cycleformation section (PWM cycle setting means) 22 is constituted to readthe set value in a register 18 and output the PWM cycle pulse with thePWM fundamental clock as (1/M).

The duty ratio formation section 24 comprises a counter that is reseteach time a PWM cycle pulse is inputted, and reads N values stored in aregister 20, measures N clocks' worth of the PWM fundamental clocks inthe PWM cycle, and outputs a drive signal (PWM-OUT) with the N/M dutyratio.

(4) and (5) in FIG. 2 are waveform characteristics that represent aPWM-modulated drive control command signal wave with an N/M duty. (4) isa control waveform with a duty ratio of N/M=1/20(5%) and (5) is acontrol waveform with a duty ratio of N/M=19/20(95%). The controlwaveform (PWM-OUT) is outputted to the drive circuit of various loads.

FIG. 3 relates to the second embodiment and, with respect to the partsthat are different from those of the embodiment in FIG. 1, the dutyratio formation section 24 comprises polarity switching means 30. Thepolarity switching means alternately outputs the PWN control pulse withthe duty ratio N/M by switching the polarity. 4A and 5A in FIG. 4 arewaveforms for which the duty ratio is controlled when the polarity ispositive. Thereupon, a control pulse (4A, 5A) for which the duty ratiois controlled is outputted in sync with a pulse ((3) in FIG. 4) that isoutputted for each PWM cycle to the positive output terminal PWM-OUT(+),and the control pulse is not outputted to the terminal PWM-OUT(−) for anegative polarity ((10A) in FIG. 4).

4B and 5B in FIG. 4 is a waveform for which the duty ratio is controlledwhen the polarity is negative. Thereupon, a control pulse (4B, 5B) forwhich the duty ratio is controlled is outputted in sync with the pulse(FIG. 4 (3)) that is outputted for each PWM cycle to the negative outputterminal PWM-OUT(−) and the control pulse is not outputted to theterminal PWM-OUT(+) for a positive polarity (FIG. 4 (10B)). 20A and 20Bin FIG. 4 are the same AC control waves comprising PWM control commandwaves (PWM-OUT(+) and PWM-OUT(−)) that are supplied to a load drivecircuit. The polarity switching means performs the aforesaid duty ratiocontrol while alternately switching the polarity of the PWM controlwaves and the AC output rendered by mixing the output of the positiveoutput terminal and the output of the negative output terminal issupplied to the load drive driver circuit.

When the PWM control command wave in FIG. 3 is inputted to the driver ofthe AC drive-type load (AC motor), the power supplied to the load can becontrolled by switching the voltage of the inverter applied to the loadat the determined duty ratio.

FIG. 5 relates to the third embodiment and shows that, unlike the secondembodiment, an AC drive frequency signal 50 is inputted to the PWMfundamental wave generation circuit 12 and the cycle of the AC drivefrequency is maintained as the PWM cycle. The load, for example, therotational speed of the AC motor can be changed by causing the AC drivefrequency to fluctuate. However, according to the embodiment in FIG. 5,the duty ratio of the PWM drive command signal supplied to the load canalso be changed in accordance with the operating state of the load.

FIG. 6 shows a control wave characteristic diagram for this embodiment.The PWM fundamental wave generation section 12 locks the PWM cycle tothe AC drive frequency so that 2*M pulses of the PWM clock signal (1)arrive in one cycle of the AC drive frequency ((30) in FIG. 6) (3).

The CPU 16 determines N for the setting of the duty value in accordancewith the operating state of the load and stores N in the register 18.The duty ratio formation section 24 counts N pulses of PWM clocks foreach PWM cycle signal (polarity switching signal) that is outputted forevery M pulses of the PWM clock and sets the duty ratio (N/M).

For each output cycle of the polarity switching signal, the duty ratioformation section 24 alternately outputs a PWM control signal with aduty ratio to the positive output terminal (PWM-OUT(+)) and the negativeoutput terminal (PWM-OUT(−)) (5A, 5B). As a result, as shown in (10) inFIG. 6, a cycle corresponding with the AC drive frequency is providedand an AC PWM control wave for which the duty ratio is controlled can beformed.

FIG. 7 shows an embodiment in which the PWM control circuit 1 in FIG. 1(or FIGS. 3 and 5) is used in a rotational speed control apparatus of amotor 74. A load operating command control signal (rotational speedindication wave signal) is formed by feeding back the detection signalfrom the motor via the PLL and synchronizing the detection signal withthe load operating state detection signal. As a result, control of theoperating state of the load, for example, of the rotational speed of themotor to increase or maintain the speed can be executed.

A variety of motors such as a stepping motor or other DC motor, or an ACmotor can be used as the motor. A hole element is provided in the motorand a detection signal is outputted in accordance with the rotationalposition of the rotor. The detection signal is inputted to a phasecomparator 78 of the PLL. A speed indication section 1 6A for the motoris supplied to the CPU 16.

The CPU 16 determines the division ratio for the indication speed from astorage table in memory and establishes the division ratio in thestorage section 80. The PLL circuit of a rotational speed indicationformation section 82 reads the division ratio from the storage section80 and divides the fundamental oscillation frequency by means of thedivision ratio.

The divided PLL frequency is supplied to the phase comparator 78 and anup or down of the rotational speed of the motor is determined inaccordance with the phase comparison result and the command value ofeither the up or down is supplied to a counter 76. The PWM clockfrequency is supplied to the counter.

FIG. 8 shows the control waveforms, where (1) represents the PWM clockfrequency in FIG. 2. (100) is the rotational speed indication wave thatis outputted by the rotational speed indication formation section 82.(102) is a detection pulse from a rotational speed sensor 70. The phasecomparator 78 outputs a phase difference signal that corresponds to thephase difference between the rotational speed indication wave anddetection pulse to the counter 76 in sync with the PWM clock pulse (1)and the counter 76 increases the period counter value (104). When thereis an increase in the counter value, the rotational speed of the motoris increased and the count value (N) is established in the PWM controlcircuit 1 by means of the counter 76. The PWM control circuit determinesthe duty ratio (N/M) from the N value and outputs the PWM controlcommand signal with the duty ratio in FIG. 1 to the motor drive section72.

Because the frequency of the detection wave from the rotation speedsensor 70 is low and the rotational speed of the motor is low, the CPU16 selects the division ratio so that a phase difference with a largervalue is produced and establishes the division ratio in the storagesection 80. Further, a down command is not outputted by the comparator78 when the rotational speed of the motor increases (FIG. 8 (104A)).

On the other hand, when there is a decrease of the rotational speed ofthe motor, that is, when the rotational speed of the motor is reducedfrom a state where the rotational speed of the motor is high as per(106) in FIG. 8, a phase difference arises between the rotational speedindication pulse and the rotational speed detection pulse as shown in(108). During this time, the count value of the counter 76 is reducedand the count value is sequentially outputted to the PWM control section1 as a down signal.

When the counter value is reduced and N is accordingly reduced, the PWMcontrol circuit 1 sets the duty ratio low. During deceleration of themotor, an up command is not outputted (106A). The CPU judges the needfor an increase or decrease in the rotational speed of the motor fromthe set speed and the motor rotational speed detection value and sets acounter count-up flag or count-down flag in the counter 76. The counterchecks the flag and executes a count-up or count-down in sync with thePWM control clock (1).

FIG. 9 relates to yet another embodiment of the present invention and,unlike the aforementioned embodiments, shows a case where a controlblock is constituted by a personal computer instead of constituting acontrol block by a logic circuit gate. The CPU 16 computes therotational speed of the motor from the detection value of the rotationalspeed sensor of the motor, compares the rotational speed computationvalue and the indication value instructed by the speed indicationsection 16A, and adjusts the duty ratio of the PWM control commandsignal as shown in FIG. 1 in accordance with the comparison result. Thatis, when the speed detection value reflects a small speed, the dutyratio (N/M) is increased and, when the speed detection value does notreflect a small speed, the duty ratio is decreased.

The PWM control system described hereinabove has the effect of beingable to stably perform PWM drive control corresponding with the PWMcycle in order to make it possible to set the duty ratio on the basis of(N/M) even when the PWM drive frequency (M) fluctuates.

1. A load drive control system, comprising: a PWM control systemcomprising PWM fundamental wave generation means for forming a PWMfundamental wave by dividing a fundamental frequency signal; PWM cyclesetting means for setting a PWM cycle on the basis of the PWMfundamental wave; duty ratio formation means for forming a duty ratio(N/M:N≦M, where M is the maximum number of clocks) in the PWM cycle; andPWM control signal output means for outputting a PWM control signal withthe duty ratio to a load drive circuit; load operational state detectionmeans; load operational state command means; a PLL circuit for dividingthe fundamental wave at a division ratio corresponding to the operatingcommand state; and comparison means for comparing the output from thePLL circuit with the load operational state detection value, wherein thecomparison result is supplied to the duty ratio formation means of thePWM system; and the PWM control signal of the duty ratio formed inaccordance with the comparison result is outputted to the load drivecircuit by the PWM control signal output means.
 2. The load drivecontrol system according to claim 1, wherein the PWM cycle setting meanssets a frequency generated by dividing the PWM fundamental wave by the Mvalue as the PWM cycle.
 3. The load drive control system according toclaim 1, further comprising control characteristic setting means fordetermining the M value and duty ratio set value (N) in accordance withthe operating state of the load.
 4. The load drive control systemaccording to claim 1, wherein the PWM fundamental wave generation meansforms a PWM fundamental frequency signal by M-dividing the fundamentalfrequency signal by means of a PLL circuit.
 5. The load drive controlsystem according to claim 1, wherein the PWM control signal output meansoutputs the AC PWM control signal by switching the polarity of theoutputted PWM control signal.
 6. The load drive control system accordingto claim 4, wherein the PWM fundamental wave generation means isconstituted to lock the PWM cycle to the cycle of the AC drive frequencysignal.
 7. canceled
 8. The load drive control system according to claim1, wherein the PWM fundamental wave generation means forms a fundamentalwave for PWM duty control by dividing the fundamental frequency signalby means of the PLL circuit.
 9. The load drive control system accordingto claim 1, wherein the PWM control signal can be formed withoutcomparison with a triangular wave.
 10. The load drive control systemaccording to claim 2, further comprising control characteristic settingmeans for determining the M value and duty ratio set value (N) inaccordance with the operating state of the load.
 11. The load drivecontrol system according to claim 2, wherein the PWM control signaloutput means outputs the AC PWM control signal by switching the polarityof the outputted PWM control signal.
 12. The load drive control systemaccording to claim 3, wherein the PWM control signal output meansoutputs the AC PWM control signal by switching the polarity of theoutputted PWM control signal.
 13. The load drive control systemaccording to claim 4, wherein the PWM control signal output meansoutputs the AC PWM control signal by switching the polarity of theoutputted PWM control signal.
 14. The load drive control systemaccording to 10, wherein the PWM control signal output means outputs theAC PWM control signal by switching the polarity of the outputted PWMcontrol signal.